Prototyping for MSX with 8 bit baby and CPLD
Update (2016/11): Prototype board now functional, althought due to pin limitations, only 4 bits is used for the MSX Data bus. Fully functional applications are still possible, but two transfers are required using this prototype (4 bits in each transfer). Demo video with a sample Chat application is available here:
Latest prototype looks like this. Note that I used a even smaller daughter dev kit (with the CPLD and jtag port) to help getting the project done.
After a few years playing with FPGAs, I thought it would be nice to work with the real thing, that is, actual computer hardware. And so I started doing this small project, which is interface one of my MSX computers with external hardware, conected into one of its slots. How simple could be that? After several attempts, and help from some more knowledgeable friends, I finally came out with a working project.
Using a cut-off prototype board (that count not fit into the MSX slot), I wired some connections to a CPLD and a LED, plugged to the MSX slot and run some OUT commands to get the LED to light up and down. Also, implemented some extra registers just for the sake of showing up how it works.
Pictures of the prototype board:
And a video of it working here:
Final VHDL code is very simple:
library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY MSXInterface IS GENERIC( data_size : INTEGER := 7); PORT ( -- these are teh signals that will connect to the MSX BUS RESET_n : IN STD_LOGIC; MREQ_n : IN STD_LOGIC; IORQ_n : IN STD_LOGIC; M1_n : IN STD_LOGIC; WR_n : IN STD_LOGIC; RD_n : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); D : INOUT STD_LOGIC_VECTOR(data_size DOWNTO 0); -- This signal will connect to the LED LED : OUT STD_LOGIC := '0'); END MSXInterface; ARCHITECTURE behavioural OF MSXInterface IS -- create the internal registers into the CPLD signal led_reg : STD_LOGIC; signal reg1 : STD_LOGIC_VECTOR(7 downto 0); signal reg2 : STD_LOGIC_VECTOR(7 downto 0); signal reg3 : STD_LOGIC_VECTOR(7 downto 0); signal reg4 : STD_LOGIC_VECTOR(7 downto 0); BEGIN -- Drive the LED with the buffered signal - LED will keep its state until it is changed by another OUT command LED <= led_reg; -- Drive the LED register with the value in the data bus and address Address bus is 0x50 led_reg <= D(0) WHEN A = X"50" AND IORQ_n = '0' AND WR_n = '0'; -- Drive the other registers in the CPLD reg1 <= D WHEN A = X"51" AND IORQ_n = '0' AND WR_n = '0'; reg2 <= D WHEN A = X"52" AND IORQ_n = '0' AND WR_n = '0'; reg3 <= D WHEN A = X"53" AND IORQ_n = '0' AND WR_n = '0'; reg4 <= D WHEN A = X"54" AND IORQ_n = '0' AND WR_n = '0'; -- Read the register from the CPLD D <= reg1 WHEN A = X"51" AND IORQ_n = '0' AND RD_n = '0' ELSE reg2 WHEN A = X"52" AND IORQ_n = '0' AND RD_n = '0' ELSE reg3 WHEN A = X"53" AND IORQ_n = '0' AND RD_n = '0' ELSE reg4 WHEN A = X"54" AND IORQ_n = '0' AND RD_n = '0' ELSE "0000000" & led_reg WHEN A = X"50" AND IORQ_n = '0' AND RD_n = '0' ELSE "ZZZZZZZZ"; end behavioural;